Design technology co-optimization for a robust 10nm solution for logic design and Sram

Vandewalle, BorisBorisVandewalleChava, BharaniBharaniChavaSakhare, SushilSushilSakhareRyckaert, JulienJulienRyckaertDusa, MirceaMirceaDusa2021-10-222021-10-222014https://imec-publications.be/handle/20.500.12860/24732Design technology co-optimization for a robust 10nm solution for logic design and SramProceedings paperhttp://spie.org/Publications/Proceedings/Paper/10.1117/12.2048079