Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

Civale, YannYannCivaleVan Huylenbroeck, StefaanStefaanVan HuylenbroeckRedolfi, AugustoAugustoRedolfiGuo, WeiWeiGuoBabaei Gavan, KhashayarKhashayarBabaei GavanJaenen, PatrickPatrickJaenenLa Manna, AntonioAntonioLa MannaBeyer, GeraldGeraldBeyerSwinnen, BartBartSwinnenBeyne, EricEricBeyne2021-10-212021-10-212013https://imec-publications.be/handle/20.500.12860/22153Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performanceProceedings paper