Sangani, DishantDishantSanganiVandemaele, MichielMichielVandemaeleTyaginov, StanislavStanislavTyaginovBury, ErikErikBuryKaczer, BenBenKaczerGielen, G.G.Gielen2026-01-292026-01-292025979-8-3315-0478-61541-7026https://imec-publications.be/handle/20.500.12860/58756With aggressive scaling of CMOS transistors, hot-carrier degradation (HCD) has re-emerged as a serious reliability concern. The understanding of HCD has shifted from a field-driven to a carrier-energy-driven phenomenon, where microscopic interactions among the carrier ensemble determine the damage rate. HCD models based on the energy-driven approach tend to be quite complex and computationally cumbersome, making their implementation in a circuit simulation environment very challenging. In this work, (i) we propose a compact abstraction of the HCD model built on the energy-driven paradigm, (ii) validate the model against extensive device-level measurements from a commercial CMOS technology, and (iii) implement the model in Verilog-A and demonstrate a good trade-off between physical accuracy and computational efficiency.engProceedings paper10.1109/IRPS48204.2025.10983543WOS:001546466200144