Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage

Anghel, C.C.AnghelHefyene, N.N.HefyeneIonescu, A. M.A. M.IonescuVermandel, MiguelMiguelVermandelBakeroot, BenoitBenoitBakerootDoutrloigne, J.J.DoutrloigneGillon, R.R.GillonFrere, S.S.FrereMaier., C.C.Maier.Mourier, Y.Y.Mourier2021-10-142021-10-142001https://imec-publications.be/handle/20.500.12860/5012Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltageProceedings paper