Delie, GillesGillesDelieDecoster, StefanStefanDecosterHermans, YannickYannickHermansMarti, GiulioGiulioMartiRenaud, VincentVincentRenaudVrancken, EviEviVranckenKenens, BartBartKenensDe Wachter, BartBartDe WachterMurdoch, GayleGayleMurdochWu, ChenChenWuPark, SeonghoSeonghoParkTokei, ZsoltZsoltTokei2026-08-212026-08-212025979-8-3315-6786-62380-9248https://imec-publications.be/handle/20.500.12860/60086We demonstrate for the first time a two metal level Ru interconnect using fully self-aligned vias (FSAV) landing on 16 nm metal pitch (MP). Mx lines are patterned using EUV-SADP and direct metal etch of Ru in a spacer is dielectric (SID) integration scheme. With a critical dimension (CD) of 8 nm Mx lines measure an average of 670 Ω/µm with a yield of >95% across a 300 mm wafer and average resistivity of 15.5 µΩ.cm extracted from TCR measurements. FSAV via performance is competitive with a measured resistance value of 14 Ω for >95% yield across the full wafer. This effort is a crucial step towards the tight pitch requirements of standard cell scaling and CFET implementation.engProceedings paper10.1109/iedm50572.2025.11353603WOS:001701480300087