Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

Severi, SimoneSimoneSeveriHenson, KirklenKirklenHensonLindsay, RichardRichardLindsayLauwers, AnneAnneLauwersPawlak, BartekBartekPawlakSurdeanu, RaduRaduSurdeanuDe Meyer, KristinKristinDe Meyer2021-10-152021-10-152004-04https://imec-publications.be/handle/20.500.12860/9580Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology nodeProceedings paper