An optimized poly-buffered LOCOS process for a 0.35 µm CMOS technology

Mieville, Jean-PaulJean-PaulMievilleRooyackers, RitaRitaRooyackersDeferm, LudoLudoDeferm2021-09-292021-09-291994https://imec-publications.be/handle/20.500.12860/257An optimized poly-buffered LOCOS process for a 0.35 µm CMOS technologyProceedings paper