Stadler, W.W.StadlerEsmark, K.K.EsmarkReynders, K.K.ReyndersZubeidat, M.M.ZubeidatGraf, M.M.GrafWilkening, W.W.WilkeningWillemen, J.J.WillemenQu, D.D.QuMettler, S.S.MettlerEtherton, M.M.EthertonNuernbergk, D.D.NuernbergkWolf, H.H.WolfGieser, H.H.GieserSoppa, W.W.SoppaDe Heyn, VincentVincentDe HeynMahadeva Iyer, NatarajanNatarajanMahadeva IyerGroeseneken, GuidoGuidoGroesenekenMorena, E.E.MorenaStella, I.I.StellaAndreini, A.A.AndreiniLitzenberger, M.M.LitzenbergerPogany, D.D.PoganyGornik, E.E.GornikFoss, C.C.FossKonrad, A.A.KonradFrank, M.M.Frank2021-10-162021-10-162005https://imec-publications.be/handle/20.500.12860/11266Test circuits for fast and reliable assessment if CDM robustness of I/O stagesJournal article