Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

Mertens, HansHansMertensRitzenthaler, RomainRomainRitzenthalerVaisman Chasin, AdrianAdrianVaisman ChasinSchram, TomTomSchramKunnen, EddyEddyKunnenHikavyy, AndriyAndriyHikavyyRagnarsson, Lars-AkeLars-AkeRagnarssonDekkers, HaroldHaroldDekkersHopf, TobyTobyHopfWostyn, KurtKurtWostynDevriendt, KatiaKatiaDevriendtChew, Soon AikSoon AikChewKim, Min-SooMin-SooKimKikuchi, YoshiakiYoshiakiKikuchiRosseel, ErikErikRosseelMannaert, GeertGeertMannaertKubicek, StefanStefanKubicekDemuynck, StevenStevenDemuynckDangol, AnishAnishDangolBosman, NielsNielsBosmanGeypen, JefJefGeypenCarolan, PatrickPatrickCarolanBender, HugoHugoBenderBarla, KathyKathyBarlaHoriguchi, NaotoNaotoHoriguchiMocuta, DanDanMocuta2021-10-232021-10-232016-12https://imec-publications.be/handle/20.500.12860/27006Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gatesProceedings paper