Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration

Mertens, HansHansMertensRitzenthaler, RomainRomainRitzenthalerPena, VanessaVanessaPenaSantoro, GaetanoGaetanoSantoroKenis, KarineKarineKenisSchulze, AndreasAndreasSchulzeDentoni Litta, EugenioEugenioDentoni LittaChew, Soon AikSoon AikChewDevriendt, KatiaKatiaDevriendtChiarella, ThomasThomasChiarellaDemuynck, StevenStevenDemuynckYakimets, DmitryDmitryYakimetsJang, DoyoungDoyoungJangSpessot, AlessioAlessioSpessotEneman, GeertGeertEnemanDangol, AnishAnishDangolLagrain, PieterPieterLagrainBender, HugoHugoBenderSun, ShiyuShiyuSunKorolik, MichaelMichaelKorolikKioussis, D.D.KioussisKim, MyungsunMyungsunKimBu, Kyung-HoKyung-HoBuChen, Shih ChungShih ChungChenCogorno, MattMattCogornoDevrajan, J.J.DevrajanMachillot, JeromeJeromeMachillotYoshida, NaomiNaomiYoshidaKim, NamsungNamsungKimBarla, KathyKathyBarlaMocuta, DanDanMocutaHoriguchi, NaotoNaotoHoriguchi2021-10-242021-10-242017https://imec-publications.be/handle/20.500.12860/28971Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstrationProceedings paperhttp://ieeexplore.ieee.org/document/8268511/