Wang, ChaohanChaohanWangCousins, JackJackCousinsFarokhnejad, AnitaAnitaFarokhnejadGarcia Bardon, MarieMarieGarcia BardonRyckaert, JulienJulienRyckaert2026-06-152026-06-152025979-8-3503-5684-70271-4302https://imec-publications.be/handle/20.500.12860/59674CMOS scaling involves more than just reducing the effective channel length—it has become increasingly complex. Aligning the circuit design ecosystem with semiconductor technology is now more critical than ever, giving rise to the Design-Technology Co-Optimization (DTCO) concept and further extending Moore’s Law. This live demonstration presents our previously published N2 nanosheet Pathfinding PDK (P-PDK) which provides insight into cutting-edge CMOS technology under the framework of DTCO. This session will cover the motivation behind developing this cutting-edge PDK, the basic flow of using the P-PDK, and the prospects of the P-PDK.engProceedings paper10.1109/iscas56072.2025.11044114WOS:001537918204181