Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Wu, LizhouLizhouWuRao, SiddharthSiddharthRaoTaouil, MottaqiallahMottaqiallahTaouilMarinissen, Erik JanErik JanMarinissenKar, Gouri SankarGouri SankarKarHamdioui, SaidSaidHamdioui2022-08-182022-07-182022-07-192022-08-1820211558-1101WOS:000805289900322https://imec-publications.be/handle/20.500.12860/40136Characterization and Fault Modeling of Intermediate State Defects in STT-MRAMProceedings paper10.23919/DATE51398.2021.9473999978-3-9819263-5-4WOS:000805289900322Electrical & electronic engineeringSTT-MRAM, MRAM, testing, embedded memory