Challenges for spacer and source/drain cavity patterning in CFET devices

Mannaert, GeertGeertMannaertMertens, HansHansMertensHosseini, MaryamMaryamHosseiniDemuynck, StevenStevenDemuynckNguyen, Vy Thi HoangVy Thi HoangNguyenChan, BTBTChanLazzarino, FredericFredericLazzarino2025-02-102023-06-262025-02-102023-05-160277-786Xhttps://imec-publications.be/handle/20.500.12860/42094Challenges for spacer and source/drain cavity patterning in CFET devicesProceedings paperhttp://dx.doi.org/10.1117/12.2658073Electrical & electronic engineering