3D Wafer level packaging: processes and materials for through silicon-vias and thin die embedding

Soussan, PhilippePhilippeSoussanSabuncuoglu Tezcan, DenizDenizSabuncuoglu TezcanIker, FrancoisFrancoisIkerRuythooren, WouterWouterRuythoorenSwinnen, BartBartSwinnenMajeed, BivraghBivraghMajeedBeyne, EricEricBeyne2021-10-182021-10-182009https://imec-publications.be/handle/20.500.12860/162623D Wafer level packaging: processes and materials for through silicon-vias and thin die embeddingProceedings paper