Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

Bock, KarlheinzKarlheinzBockRuss, ChristianChristianRussBadenes, GonçalGonçalBadenesGroeseneken, GuidoGuidoGroesenekenDeferm, LudoLudoDeferm2021-09-302021-09-301997https://imec-publications.be/handle/20.500.12860/1748Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technologyProceedings paper