Circuit-level modeling of Finfet sub-threshold slope and DIBL mismatch beyond 22nm

Royer Del Barrio, PabloPabloRoyer Del BarrioZuber, PaulPaulZuberCheng, BinjieBinjieChengAsenov, AsenAsenAsenovLopez-Vallejo, M.M.Lopez-Vallejo2021-10-212021-10-212013https://imec-publications.be/handle/20.500.12860/23020Circuit-level modeling of Finfet sub-threshold slope and DIBL mismatch beyond 22nmProceedings paper