Design enablement of CFET devices for sub-2nm CMOS nodes

Zografos, OdysseasOdysseasZografosChehab, BilalBilalChehabSchuddinck, PieterPieterSchuddinckMirabelli, GioeleGioeleMirabelliKakarla, NaveenNaveenKakarlaXiang, YangYangXiangWeckx, PieterPieterWeckxRyckaert, JulienJulienRyckaert2023-04-282022-07-172022-09-062023-04-282022-05-191530-1591WOS:000819484300006https://imec-publications.be/handle/20.500.12860/40127Design enablement of CFET devices for sub-2nm CMOS nodesProceedings paper10.23919/DATE54114.2022.9774720978-3-9819263-6-1WOS:000819484300006Electrical & electronic engineeringCMOS scaling, CFET