Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

Arutchelvan, GouthamGouthamArutchelvanChiarella, ThomasThomasChiarellaArimura, HiroakiHiroakiArimuraVeloso, AnabelaAnabelaVelosoJourdain, AnneAnneJourdainDentoni Litta, EugenioEugenioDentoni LittaHoriguchi, NaotoNaotoHoriguchiMitard, JeromeJeromeMitard2024-01-252023-02-022024-01-252022-10-010000-0000https://imec-publications.be/handle/20.500.12860/41054Impact of Back-side Power Delivery Network Layout on the FinFET Device PerformanceProceedings paperElectrical & electronic engineering