Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances

Noori, AtifAtifNooriBalseanu, MihaelaMihaelaBalseanuBoelen, PieterPieterBoelenCockburn, AndrewAndrewCockburnDemuynck, StevenStevenDemuynckFelch, SusanSusanFelchGandikota, SrinivasSrinivasGandikotaGelatos, jerryjerryGelatosKhandelwal, AmitAmitKhandelwalKittl, JorgeJorgeKittlLauwers, AnneAnneLauwersLee, Wen-ChinWen-ChinLeeLei, JianxinJianxinLeiMandrekar, TusharTusharMandrekarSchreutelkamp, RobRobSchreutelkampShah, KavitaKavitaShahThompson, ScottScottThompsonVerheyen, PeterPeterVerheyenWang, Ching-YaChing-YaWangXia, Li-QunLi-QunXiaArghavani, RezaRezaArghavani2021-10-172021-10-1720080018-9383https://imec-publications.be/handle/20.500.12860/14223Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistancesJournal article