Gupta, MihirMihirGuptaXiang, YangYangXiangGarcia Redondo, FernandoFernandoGarcia RedondoCai, KaimingKaimingCaiAbdi, DawitDawitAbdiLiu, H. -H.H. -H.LiuRao, SiddharthSiddharthRaoHiblot, GaspardGaspardHiblotCouet, SebastienSebastienCouetGarcia Bardon, MarieMarieGarcia BardonHellings, GeertGeertHellings2026-05-042026-05-0420232380-9248https://imec-publications.be/handle/20.500.12860/59271The Voltage-Gated Spin-Orbit-Torque (VGSOT) MRAM is a unique multi-bit SOT-MRAM implementation with the aid of voltage-controlled magnetic anisotropy (VCMA). In this paper, we explore the Power-PerformanceArea scaling potential of VGSOT for last-level cache (LLC) towards 14-Å node, and profile the required device design space based on a hardware-validated compact model. We highlight the outstanding bit density of VGSOT-4MTJ up to ~ 3× of iso-node SRAM, which in an LLC-relevant, (16 – 32) MB memory macro brings down the global interconnect length by 40 %; this in turn translates to max. 60 % and 30 % overall delay and energy reduction, respectively, over SRAM. We nonetheless emphasize the essential all-aspect technology co-optimization of SOT track (in resistivity and Spin Hall angle) and MTJ stack (in VCMA efficiency) for unlocking the desired selective writing in a multi-bit VGSOT cell. We conclude that the multi-bit VGSOT provides an alternative, density-enabled, interconnect-centric scaling route for LLC.engProceedings paper10.1109/iedm45741.2023.10413886WOS:001693000200226