12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices

Kim, Min-SooMin-SooKimHarada, N.N.HaradaKikuchi, YoshiakiYoshiakiKikuchiBoemmels, JuergenJuergenBoemmelsMitard, JeromeJeromeMitardHuynh Bao, TrongTrongHuynh BaoMatagne, PhilippePhilippeMatagneTao, ZhengZhengTaoLi, WaikinWaikinLiDevriendt, KatiaKatiaDevriendtRagnarsson, Lars-AkeLars-AkeRagnarssonLorant, ChristopheChristopheLorantSebaai, FaridFaridSebaaiPorret, ClémentClémentPorretRosseel, ErikErikRosseelDangol, AnishAnishDangolBatuk, DmitryDmitryBatukMartinez Alanis, Gerardo TadeoGerardo TadeoMartinez AlanisGeypen, JefJefGeypenJourdan, NicolasNicolasJourdanSepulveda Marquez, AlfonsoAlfonsoSepulveda MarquezPuliyalil, HarinarayananHarinarayananPuliyalilJamieson, GeraldineGeraldineJamiesonvan der Veen, MarleenMarleenvan der VeenTeugels, LieveLieveTeugelsEl-Mekki, ZaidZaidEl-MekkiAltamirano Sanchez, EfrainEfrainAltamirano SanchezLi, Y.Y.LiNakamura, H.H.NakamuraMocuta, DanDanMocutaMatsuoka, F.F.Matsuoka2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/3329712-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devicesProceedings paperhttps://ieeexplore.ieee.org/document/8776532