Interconnect Design-Technology Co-Optimization for Sub-3nm Technology Nodes

Baert, RogierRogierBaertCiofi, IvanIvanCiofiPatli, SudhirSudhirPatliZografos, OdysseasOdysseasZografosSarkar, SatadruSatadruSarkarChehab, BilalBilalChehabJang, DoyoungDoyoungJangSpessot, AlessioAlessioSpessotRyckaert, JulienJulienRyckaertTokei, ZsoltZsoltTokei2021-10-282021-10-282020https://imec-publications.be/handle/20.500.12860/34670Interconnect Design-Technology Co-Optimization for Sub-3nm Technology NodesProceedings paper