Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node

Pan, ChenyunChenyunPanRaghavan, PraveenPraveenRaghavanCeyhan, AhmetAhmetCeyhanCatthoor, FranckyFranckyCatthoorTokei, ZsoltZsoltTokeiNaeemi, AzadAzadNaeemi2021-10-222021-10-2220150018-9383https://imec-publications.be/handle/20.500.12860/25729Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology nodeJournal articlehttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7061953