Ryckaert, JulienJulienRyckaertNa, Myung HeeMyung HeeNaWeckx, PieterPieterWeckxJang, DoyoungDoyoungJangSchuddinck, PieterPieterSchuddinckChehab, BilalBilalChehabPatli, SudhirSudhirPatliSarkar, SatadruSatadruSarkarZografos, OdysseasOdysseasZografosBaert, RogierRogierBaertVerkest, DiederikDiederikVerkest2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/33918Enabling sub-5nm CMOS technology scaling thinner and taller!Proceedings paper