A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G(max)-Core

Yun, ByeonghunByeonghunYunPark, Dae-WoongDae-WoongParkMahmood, Hafiz UsmanHafiz UsmanMahmoodKim, DoyoonDoyoonKimLee, Sang-GugSang-GugLee2022-09-272021-11-022022-09-2720210018-9480WOS:000662675000010https://imec-publications.be/handle/20.500.12860/37880A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G(max)-CoreJournal article10.1109/TMTT.2021.3066972WOS:000662675000010ALGORITHMIC DESIGNAMPLIFIER DESIGNSPECTROSCOPY