FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)

Tao, ZhengZhengTaoLi, WaikinWaikinLiKim, Min-SooMin-SooKimDevriendt, KatiaKatiaDevriendtLorant, ChristopheChristopheLorantSebaai, FaridFaridSebaaiPorret, ClémentClémentPorretRosseel, ErikErikRosseelSepulveda Marquez, AlfonsoAlfonsoSepulveda MarquezJourdan, NicolasNicolasJourdanKikuchi, YoshiakiYoshiakiKikuchiBoemmels, JuergenJuergenBoemmelsMitard, JeromeJeromeMitardMatagne, PhilippePhilippeMatagneRagnarsson, Lars-AkeLars-AkeRagnarssonDangol, AnishAnishDangolBatuk, DmitryDmitryBatukMartinez Alanis, Gerardo TadeoGerardo TadeoMartinez AlanisGeypen, JefJefGeypenAltamirano Sanchez, EfrainEfrainAltamirano SanchezLee, JamesJamesLeeLi, YiSuoYiSuoLiKanazawa, KenichiKenichiKanazawaHarada, NozomuNozomuHaradaMasuoka, FujioFujioMasuoka2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/34109FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)Meeting abstract