Zhao, PengPengZhaoLim, Yu DianYu DianLimLi, HongyuHongyuLiLikforman, Jean-PierreJean-PierreLikformanGuidoni, LucaLucaGuidoniDesormeaux, Lilay GrosLilay GrosDesormeauxTan, Chuan SengChuan SengTan2026-06-032026-06-0320232380-9248https://imec-publications.be/handle/20.500.12860/59527We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored.engProceedings paper10.1109/iedm45741.2023.10413875WOS:001693000200215