Challenges and opportunities for vertical nanowire FETs: device design and fabrication

Veloso, AnabelaAnabelaVelosoMatagne, PhilippePhilippeMatagneHuynh Bao, TrongTrongHuynh BaoEneman, GeertGeertEnemanLoo, RogerRogerLooWostyn, KurtKurtWostynBrus, StephanStephanBrusBoemmels, JuergenJuergenBoemmelsMocuta, DanDanMocutaRyckaert, JulienJulienRyckaert2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/32167Challenges and opportunities for vertical nanowire FETs: device design and fabricationProceedings paperhttp://www.ssdm.jp/SSDM2018_TechnicalProgram-All_Sep11-13.pdf?d=20180824