Wang, BowenBowenWangAkhunov, KhakimKhakimAkhunovOh, HyungrockHyungrockOhGarcia Redondo, FernandoFernandoGarcia RedondoChen, YukaiYukaiChenSharma, ArvindArvindSharmaSun, JiacongJiacongSunGamage, SahanSahanGamageRosmeulen, MaartenMaartenRosmeulenMahato, SwarajSwarajMahatoKishore, RishabhRishabhKishoreSubhechha, SubhaliSubhaliSubhechhaKulkarni, JaydeepJaydeepKulkarniVerhelst, MarianMarianVerhelstBiswas, DwaipayanDwaipayanBiswasGarcia Bardon, MarieMarieGarcia BardonDehaene, WimWimDehaeneRyckaert, JulienJulienRyckaert2026-05-282026-05-282025979-8-3503-5684-70271-4302https://imec-publications.be/handle/20.500.12860/59452The demand for high-capacity and energy-efficient memory solutions has surged in the era of data-centric computing, particularly for Artificial Intelligence (AI) and Machine Learning (ML) workloads. This paper introduces a novel memory architecture leveraging Charge-Coupled Device (CCD) technology, engineered in a sequential-access block memory configuration, to enhance Compute-near-Memory (CnM) systems. We propose an optimized 3D IGZO CCD block memory as an on-chip weight buffer for high-capacity CnM systems. Our approach achieves 2.95−131.26× improvement in area efficiency and 1.32−4.33× improvement in energy efficiency compared to SRAM solutions.engProceedings paper10.1109/iscas56072.2025.11043541WOS:001537918202028ACCESS