Shrinking from 0.25 μm down to 0.12 μm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs

Dieudonné, F.F.DieudonnéHaendler, S.S.HaendlerJomaah, J.J.JomaahRaynaud, C.C.RaynaudDe Meyer, KristinKristinDe Meyervan Meer, HansHansvan MeerBalestra, F.F.Balestra2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/6283Shrinking from 0.25 μm down to 0.12 μm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETsProceedings paper