A low power high speed parallel concatenated turbo-decoding architecture

Bougard, BrunoBrunoBougardGiulietti, AlexandreAlexandreGiuliettiDesset, ClaudeClaudeDessetVan der Perre, LiesbetLiesbetVan der PerreCatthoor, FranckyFranckyCatthoor2021-10-152021-10-152003-09https://imec-publications.be/handle/20.500.12860/7249A low power high speed parallel concatenated turbo-decoding architectureProceedings paper