Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm

Weckx, PieterPieterWeckxRyckaert, JulienJulienRyckaertPutcha, VamsiVamsiPutchaDe Keersgieter, AnAnDe KeersgieterBoemmels, JuergenJuergenBoemmelsSchuddinck, PieterPieterSchuddinckJang, DoyoungDoyoungJangYakimets, DmitryDmitryYakimetsGarcia Bardon, MarieMarieGarcia BardonRagnarsson, Lars-AkeLars-AkeRagnarssonRaghavan, PraveenPraveenRaghavanKim, Ryan Ryoung hanRyan Ryoung hanKimSpessot, AlessioAlessioSpessotVerkest, DiederikDiederikVerkestMocuta, AndaAndaMocuta2021-10-242021-10-242017https://imec-publications.be/handle/20.500.12860/29917Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nmProceedings paperhttp://ieeexplore.ieee.org/document/8268430/