3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

Das, SudiptaSudiptaDasRiedel, SamuelSamuelRiedelBertuletti, MarcoMarcoBertulettiBenini, LucaLucaBeniniBrunion, MoritzMoritzBrunionRyckaert, JulienJulienRyckaertMyers, JamesJamesMyersBiswas, DwaipayanDwaipayanBiswasMilojevic, DragomirDragomirMilojevic2024-11-042024-09-212024-11-042024979-8-3503-3100-40271-4302WOS:001268541104058https://imec-publications.be/handle/20.500.12860/445493D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCsProceedings paper10.1109/ISCAS58744.2024.10558687979-8-3503-3099-1WOS:001268541104058