Logic scaling assessment in 20nm and beyond under electrical and litho constraints

Badaroglu, MustafaMustafaBadarogluGarcia Bardon, MarieMarieGarcia BardonDobrovolny, PetrPetrDobrovolnyZuber, PaulPaulZuberMiranda Corbalan, MiguelMiguelMiranda Corbalan2021-10-202021-10-202012https://imec-publications.be/handle/20.500.12860/20327Logic scaling assessment in 20nm and beyond under electrical and litho constraintsProceedings paper