On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

Vais, AbhitoshAbhitoshVaisMartens, KoenKoenMartensLin, DennisDennisLinCollaert, NadineNadineCollaertMocuta, AndaAndaMocutaDe Meyer, KristinKristinDe MeyerThean, AaronAaronThean2021-10-222021-10-2220150167-9317https://imec-publications.be/handle/20.500.12860/26029On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devicesJournal articlehttp://www.sciencedirect.com/science/article/pii/S0167931715003123