Understanding the optimization of sub-45nm FinFET devices for ESD applications

Tremouilles, DavidDavidTremouillesThijs, StevenStevenThijsRuss, ChristianChristianRussSchneider, J.J.SchneiderDuvvury, CharvarkaCharvarkaDuvvuryCollaert, NadineNadineCollaertLinten, DimitriDimitriLintenScholz, MirkoMirkoScholzJurczak, GosiaGosiaJurczakGossner, HaraldHaraldGossnerGroeseneken, GuidoGuidoGroeseneken2021-10-162021-10-162007https://imec-publications.be/handle/20.500.12860/12993Understanding the optimization of sub-45nm FinFET devices for ESD applicationsProceedings paper