Radu, I.I.RaduNguyen, B-Y.B-Y.NguyenChang, C-H.C-H.ChangNeve, C. RodaC. RodaNeveGaudin, G.G.GaudinBesnard, G.G.BesnardBatude, P.P.BatudeLoup, V.V.LoupBrunet, L.L.BrunetVandooren, AnneAnneVandoorenHoriguchi, NaotoNaotoHoriguchi2026-04-272026-04-2720232380-9248https://imec-publications.be/handle/20.500.12860/59223A review of wafer-level stacking technology providing a ultra thin and uniform single-crystalline silicon film onto a device wafer is reported in this paper. Smart Cut™ technology has been adapted at low temperatures for the transfer of a thin Si layer - ready for device fabrication. The surface micro-roughness is below 0.2nm and film thickness uniformity of 0.4nm within wafer and wafer-to-wafer measurements. Combining with low temperature device processing, the sequential manufacturing of 3D devices is demonstrated. Although the maximum temperature of the sequential 3D process does not exceed 500°C, the transistor characteristics are preserved. In this paper we report for the first time demonstration of Smart Cut layer stacking below 400°C.engProceedings paper10.1109/iedm45741.2023.10413807WOS:001693000200147