A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

Collaert, NadineNadineCollaertAoulaiche, MarcMarcAoulaicheDe Wachter, BartBartDe WachterRakowski, MichalMichalRakowskiRedolfi, AugustoAugustoRedolfiBrus, StephanStephanBrusDe Keersgieter, AnAnDe KeersgieterHoriguchi, NaotoNaotoHoriguchiAltimime, LaithLaithAltimimeJurczak, GosiaGosiaJurczak2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/16899A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°CProceedings paper