Chen, ZhuoZhuoChenKim, Hyun-CheolHyun-CheolKimZheng, WeiWeiZhengIzmailov, RomanRomanIzmailovTruijen, BrechtBrechtTruijenSubhechha, SubhaliSubhaliSubhechhaWalke, AmeyAmeyWalkeVaisman Chasin, AdrianAdrianVaisman ChasinPopovici, Mihaela IoanaMihaela IoanaPopoviciLi, JieJieLiKruv, AnastasiiaAnastasiiaKruvTang, HongweiHongweiTangXi, FengbenFengbenXiVan den Bosch, GeertGeertVan den BoschRosmeulen, MaartenMaartenRosmeulenRonchi, NicoloNicoloRonchiAfanasiev, ValeriValeriAfanasievVan Houdt, JanJanVan Houdt2026-05-182026-05-1820242380-9248https://imec-publications.be/handle/20.500.12860/59419We fabricate ALD Oxide-Semiconductor Channel (OSC) FeFETs on 300-mm wafers. New design strategies of OSC FeFETs by La:HZO/IGZO interfacial engineering and IGZO channel thickness/length scaling are implemented to achieve high endurance and faster erase. The impact of IGZO composition is investigated, revealing that In-poor IGZO improves both the Memory Window (MW) and Vt stability. High MW and state-of-art endurance (>1010 cycles) are demonstrated in novel dual-composition-channel FeFETs. With all layers grown by ALD, this advanced stack is promising for the 3D integration of OSC FeFETs in high-endurance, low-latency, and non-destructive-read memories.engNovel Design Strategy for High-Endurance (>10<SUP>10</SUP>) and Fast-Erase Oxide-Semiconductor Channel FeFETProceedings paper10.1109/iedm50854.2024.10873449WOS:001692734400131