Roy, SyamashreeSyamashreeRoyThiam, ArameArameThiamSah, KaushikKaushikSahFeurprier, YannickYannickFeurprierFukui, NobuyukiNobuyukiFukuiNafus, KathleenKathleenNafusMiyaguchi, KenichiKenichiMiyaguchiVan Den Heuvel, DieterDieterVan Den HeuvelBaskaran, BalakumarBalakumarBaskaranBekaert, JoostJoostBekaertCross, AndrewAndrewCrossDusa, MirceaMirceaDusaBlanco, VictorVictorBlanco2026-01-192026-01-192024978-1-5106-7213-00277-786Xhttps://imec-publications.be/handle/20.500.12860/58669As the semiconductor industry progresses towards the 2nm logic technology node in pursuit of improved chip performance and density, the demand for minimum pitch scaling in the back-end-of-line (BEOL) interconnect becomes crucial. Imec N3 logic design rules defined a minimum Metal 2 (M2) layer pitch of 30 nm, representing 2nm technology nodes. To further enhance semiconductor integrated circuit performance, attention is shifting towards advanced mask materials for current 0.33 NA EUV scanners. Low-n masks have been shown to improve extreme ultraviolet (EUV) imaging performance in terms of Local-CDU (LCDU), reduced mask 3D effects and improved optical contrast compared to a Tabased mask. In our study, we observed notable enhancements in optical contrast for real logic designs using a low-n mask. Our findings demonstrate an impressive LCDU of 5.5 nm and CGDU of 5.5 nm for Place’n’Route (PnR) structures at a pitch of 32. Furthermore, we successfully printed tip-to-tip (T2T) features as small as 20 nm on the wafer for regular tip-to-tip structures that didn’t get any Optical proximity Correction (OPC). These advancements mark significant progress towards manufacturability and developing a holistic patterning approach for random logic metal with EUV.enBright-FieldLow-nReal Logic designPnRSRAMLCDUGCDUScience & TechnologyTechnologyPhysical SciencesProceedings paper10.1117/12.3010868WOS:001215458300032