Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM

Han, Jin-WooJin-WooHanKim, JungsikJungsikKimBeery, DafnaDafnaBeeryBozdag, K. DenizK. DenizBozdagCuevas, PeterPeterCuevasLevi, AmitayAmitayLeviTain, IrwinIrwinTainTran, KhaiKhaiTranWalker, Andrew J.Andrew J.WalkerVadakupudhu Palayam, SenthilSenthilVadakupudhu PalayamArreghini, AntonioAntonioArreghiniFurnemont, ArnaudArnaudFurnemontMeyappan, M.M.Meyappan2022-12-012021-11-022022-05-202022-06-282022-12-0120210018-9383WOS:000612147300012https://imec-publications.be/handle/20.500.12860/38144Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAMJournal article10.1109/TED.2020.3045966WOS:000612147300012