Activity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs

Sathanur, AshokaAshokaSathanurHuisken, JosJosHuiskenStuijt, JanJanStuijtde Groot, HarmkeHarmkede Groot2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/17951Activity profile driven simultaneous Vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designsProceedings paper