Stadler, WolfgangWolfgangStadlerEsmark, K.K.EsmarkReynders, K.K.ReyndersZuhbeidat, M.M.ZuhbeidatGraf, M.M.GrafWilkening, W.W.WilkeningWillemen, J.J.WillemenQu, S.S.QuSettler, S.S.SettlerEtherton, M.M.EthertonNuernbergk, D.D.NuernbergkWolf, H.H.WolfGieser, H.H.GieserSoppa, W.W.SoppaDe Heyn, VincentVincentDe HeynMahadeva Iyer, NatarajanNatarajanMahadeva IyerGroeseneken, GuidoGuidoGroesenekenMorena, E.E.MorenaStella, R.R.StellaAndreini, A.A.AndreiniLitzenberger, M.M.LitzenbergerPogany, D.D.PoganyGornik, E.E.GornikFoss, C.C.FossKonrad, A.A.KonradFrank, M.M.Frank2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/8177Test circuits for fast and reliable assessment of CDM robustness of I/O stagesProceedings paper