Browsing by author "Barat, F."
Now showing items 1-11 of 11
-
Clustered LO buffer organisation for low energy embedded processors
Jayapala, Murali; Barat, F.; Vander Aa, Tom; De Coninck, G; Catthoor, Francky; Corporaal, Henk (2002) -
Clustered loop buffer organization for low energy VLIW embedded processors
Jayapala, Murali; Barat, F.; Vander Aa, Tom; Catthoor, Francky; Corporaal, Henk; Deconinck, G. (2005-06) -
Instruction buffering exploration for low energy embedded processors
Vander Aa, Tom; Jayapala, Murali; Barat, F.; Deconinck, G.; Lauwereins, Rudy; Corporaal, Henk; Catthoor, Francky (2003) -
Instruction buffering exploration for low energy embedded processors
Vander Aa, Tom; Jayapala, Murali; Barat, F.; Deconinck, G.; Lauwereins, Rudy; Corporaal, Henk; Catthoor, Francky (2005) -
L0 buffer energy optimisation through scheduling and exploration
Jayapala, Murali; Vander Aa, Tom; Barat, F.; Deconinck, G.; Catthoor, Francky; Corporaal, Henk (2004-03) -
L0 cluster synthesis and operation shuffling
Jayapala, Murali; Vander Aa, Tom; Barat, F.; Catthoor, Francky; Corporaal, Henk; Deconinck, G. (2004-09) -
Low energy clustered instruction fetch and split loop cache architecture for long instruction word processors
Jayapala, Murali; Barat, F.; Op de beeck, Pieter; Catthoor, Francky; De Coninck, G. (2001) -
Low power coarse-grained reconfigurable instruction set processor
Barat, F.; Jayapala, M.; Vander Aa, Tom; Lauwereins, Rudy; Deconinck, G.; Corporaal, Henk (2003) -
Methodology for building processor design space exploration
Barat, F.; Vander Aa, Tom; Jayapala, Murali; Deconinck, G.; Lauwereins, Rudy; Corporaal, Henk (2005) -
Reconfigurable instruction set processors from a hardware/software perspective
Barat, F.; Lauwereins, Rudy; Deconinck, G. (2002) -
Software transformations to reduce instruction memory power consumption using a loop buffer
Vander Aa, Tom; Barat, F.; Jayapala, Murali; Corporaal, Henk; Catthoor, Francky; Deconinck, Geert (2003)