Browsing by author "Wambacq, Piet"
Now showing items 21-40 of 314
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A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI
Balamurali, Sriram; Mangraviti, Giovanni; Zong, Zhiwei; Wambacq, Piet; Craninckx, Jan (2023) -
A 130GHz Two-Stage Common-Base Power Amplifier in 250nm InP
Banerjee, Aritra; Wambacq, Piet (2022) -
A 135-155 GHz 9.7 %/16.6 % DC-RF/DC-EIRP Efficiency Frequency Multiply-by-9 FMCW Transmitter in 28 nm CMOS
Park, Sehoon; Park, Dae-Woong; Vaesen, Kristof; Kankuppe Raghavendra Swamy, Anirudh Praveen; van Liempd, Barend; Wambacq, Piet; Craninckx, Jan (2021) -
A 140 GHz T/R Front-End Module in 22 nm FD-SOI CMOS
Tang, Xinyan; Nguyen, Johan; Mangraviti, Giovanni; Zong, Zhiwei; Wambacq, Piet (2021) -
A 145GHz FMCW-radar transceiver in 28nm CMOS
Visweswaran, Akshay; Vaesen, Kristof; Sinha, Siddhartha; Ocket, Ilja; Glassee, Miguel; Desset, Claude; Bourdoux, André; Wambacq, Piet (2019) -
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS
Malki, Badr; Verbruggen, Bob; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2015) -
A 150kHz-80MHz BW discrete-time analog baseband for aoftware-defined-radio receivers using a 5th-order IIR LPF, active FIR and a 10 bit 300 MS/s ADC in 28nm CMOS
Malki, Badr; Verbruggen, Bob; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2016) -
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2018-04) -
A 1st Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC
Yasue, Toshio; Frazzica, Fortunato; Spagnolo, Annachiara; Bello, David San Segundo; De Bock, Maarten; Wambacq, Piet; Craninckx, Jan (2020) -
A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS
Verbruggen, Bob; Craninckx, Jan; Kuijk, Maarten; Wambacq, Piet; Van der Plas, Geert (2009) -
A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS
Verbruggen, Bob; Craninckx, Jan; Kuijk, Maarten; Wambacq, Piet; Van der Plas, Geert (2008-02) -
A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm Digital CMOS
Verbruggen, Bob; Craninckx, Jan; Kuijk, Maarten; Wambacq, Piet; Van der Plas, Geert (2010) -
A 2.6mW 6b 2.2GS/s 4-times interleaved fully-dynamic pipelined ADC in 40nm digital CMOS
Verbruggen, Bob; Craninckx, Jan; Kuijk, Maarten; Wambacq, Piet; Van der Plas, Geert (2010) -
A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier
Wu, Linkun; San Segundo Bello, David; Coppejans, Philippe; Craninckx, Jan; Wambacq, Piet; Borremans, Jonathan (2016) -
A 21 dBm IQ digital transmitter using stacked output stage on 28 nm Bulk CMOS technology
Gaber, Wagdy; Wambacq, Piet; Craninckx, Jan; Ingels, Mark (2017) -
A 22-29 GHz voltage-biased LC-VCO with suppressed flicker noise over tuning range in 22nm FD-SOI
Zong, Zhiwei; Mangraviti, Giovanni; Wambacq, Piet (2019) -
A 22.5-27.7GHz fast-lock bang-bang digital PLL in 28nm CMOS for millimeter-wave communication with 220fs RMS jitter
Tsai, Cheng-Hsueh; Pepe, Federico; Mangraviti, Giovanni; Zong, Zhiwei; Craninckx, Jan; Wambacq, Piet (2019) -
A 23 GHz low-phase-noise transformer-feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz
Zong, Zhiwei; Tsai, Cheng-Hsueh; Pepe, Federico; Mangraviti, Giovanni; Liu, Yao; Shi, Qixian; Parvais, Bertrand; Wambacq, Piet (2018) -
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-G(max) Gain Boosting Technique
Park, Dae-Woong; Utomo, Dzuhri Radityo; Hong, Jong-Phil; Vaesen, Kristof; Wambacq, Piet; Lee, Sang-Gug (2020) -
A 28 GHz front-end module with T/R switch achieving 17.2 dBm P-sat, 21.5% PAE(max) and 3.2 dB NF in 22 nm FD-SOI for 5G communication
Liu, Yao; Tang, Xinyan; Mangraviti, Giovanni; Khalaf, Khaled; Zhang, Yang; Wu, Wei-Min; Chen, Shih-Hung; Debaillie, Bjorn; Wambacq, Piet (2020)