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Layout scaling of Si1-xGex pFETs

dc.contributor.authorEneman, Geert
dc.contributor.authorYamaguchi, Shinpei
dc.contributor.authorOrtolland, C.
dc.contributor.authorTakeoka, Shinji
dc.contributor.authorKobayashi, M.
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorHikavyy, Andriy
dc.contributor.authorMitard, Jerome
dc.contributor.authorLoo, Roger
dc.contributor.authorHoffmann, Thomas Y.
dc.date.accessioned2021-10-19T13:26:54Z
dc.date.available2021-10-19T13:26:54Z
dc.date.issued2011
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18888
dc.sourceIIOimport
dc.titleLayout scaling of Si1-xGex pFETs
dc.typeJournal article
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorHikavyy, Andriy
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorLoo, Roger
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecHikavyy, Andriy::0000-0002-8201-075X
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2544
dc.source.endpage2550
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue8
dc.source.volume58
imec.availabilityPublished - open access


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