Efficient Backside Power Delivery for High-Performance Computing Systems

Abstract

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-W/mm(2) power-density target for high-performance computing (HPC) systems, a 25-high-Q-factor (300 MHz), 150-mu m-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-mu m VDD-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-mu m-horizontal-pitch nano-through-silicon via (nTSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency eta = 83% can be obtained for 1-W/mm(2) power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.