Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

Abstract

Nano-ridge engineering (NRE) is a novel method to monolithically integrate III-V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 10(6).cm(-2) in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices-consisting of several nano-ridges in parallel-were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency f(t) of similar to 17 GHz was achieved. These results show the potential of NRE III-V devices for hybrid III-V/CMOS technology for emerging RF applications.