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dc.contributor.authorAlinezhad Chamazcoti, Saeideh
dc.contributor.authorGupta, Mohit
dc.contributor.authorOh, Hyungrock
dc.contributor.authorEvenblij, Timon
dc.contributor.authorCatthoor, Francky
dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2023-05-24T07:04:03Z
dc.date.available2022-12-26T03:09:52Z
dc.date.available2023-05-24T07:04:03Z
dc.date.issued2023
dc.identifier.issn1549-8328
dc.identifier.otherWOS:000896622900001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40913.3
dc.sourceWOS
dc.titleExploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
dc.typeJournal article
dc.contributor.imecauthorAlinezhad Chamazcoti, Saeideh
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorOh, Hyungrock
dc.contributor.imecauthorEvenblij, Timon
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecOh, Hyungrock::0000-0001-5244-5755
dc.contributor.orcidimecEvenblij, Timon::0000-0002-5337-0617
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.contributor.orcidimecAlinezhad Chamazcoti, Saeideh::0000-0002-0097-6375
dc.contributor.orcidimecPerumkunnil, Manu::0000-0002-0029-6548
dc.date.embargo9999-12-31
dc.identifier.doi10.1109/TCSI.2022.3222573
dc.source.numberofpages14
dc.source.peerreviewyes
dc.source.beginpage733
dc.source.endpage746
dc.source.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
dc.source.issue3
dc.source.volume70
imec.availabilityPublished - imec


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