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dc.contributor.authorChamazcoti, Saeideh Alinezhad
dc.contributor.authorGupta, Mohit
dc.contributor.authorOh, Hyungrock
dc.contributor.authorEvenblij, Timon
dc.contributor.authorCatthoor, Francky
dc.contributor.authorKomalan, Manu Perumkunnil
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2022-12-26T03:09:52Z
dc.date.available2022-12-26T03:09:52Z
dc.date.issued2022-NOV 28
dc.identifier.issn1549-8328
dc.identifier.otherWOS:000896622900001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40913
dc.sourceWOS
dc.titleExploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
dc.typeJournal article
dc.typeJournal article (pre-print)
dc.contributor.imecauthorChamazcoti, Saeideh Alinezhad
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorOh, Hyungrock
dc.contributor.imecauthorEvenblij, Timon
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorKomalan, Manu Perumkunnil
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecOh, Hyungrock::0000-0001-5244-5755
dc.contributor.orcidimecEvenblij, Timon::0000-0002-5337-0617
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.identifier.doi10.1109/TCSI.2022.3222573
dc.source.numberofpages14
dc.source.peerreviewyes
dc.source.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
imec.availabilityUnder review


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